PPT ON VHDL AND DIGITAL CIRCUIT DESIGN

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VHDL And Digital Circuit Design  Presentation Transcript

1.VHDL & Digital Circuit Design

2.Central Electronics Engineering Research Institute, popularly known as CEERI, is a constitute establishment of the Council of Scientific and Industrial Research (CSIR), New Delhi. The first Indian Prime Minister Pt. Jawaharlal Nehru laid the foundation stone of the institute on 21st September 1953. The actual R and D work started towards the end of the 1958. The institute has since then blossomed into a center for development of technology and for advanced research in electronics. Over the years the institute has developed a number of products and processes and has established facilities to meet the emerging needs of electronics industry.

3.CEERI pilani is a pioneer research institute in the country. Since it’s inception it has been working for the growth of electronics in the country and has establish the required infrastructure and well experienced men power for undertaking R and D in the following three major areas:
-Electronics System Area
-Semiconductor Devices Area
-Microwave Tubes Area

4.Contents
Introduction to VLSI
Introduction to VHDL
Modeling Digital System
Basic VHDL Concepts
VHDL features
Modeling the Dataflow way
Modeling the Structurural way
Modeling the Behavior way
Result

5.VLSI design involves translating the given specifications into geometrical patterns that are used in fabrication chips.
 This translation task is very complex and cannot be accomplished in one step. It is accomplished through a succession of translation steps of manageable complexity. Each translation step translates more abstract (less detailed) design description into less abstract (more detailed) design representation.
 Abstractions are the means of representing various views of the design with varying amounts of details.

6.VHSIC Hardware
Description Language

7.VHDL is a programming language that allows one to model and develop complex digital systems in a dynamic envirornment.
Object Oriented methodology for you C people can be observed  -- modules can be used and reused.
Allows you to designate in/out ports (bits) and specify behavior or response of the system.

8.VHDL Libraries
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_signed.all;
Use ieee.std_logic_unsigned.all;

9.Data Types

10. Entity
Define inputs and outputs
Example:

11.Architecture
Define functionality of the chip

12. VHDL features
Case insensitive
inputa, INPUTA and InputA are refer to same variable
Comments
‘--’ until end of line
If you want to comment multiple lines, ‘--’ need to be put at the beginning of every single line
Statements are terminated by ‘;’
Signal assignment:
‘<=’
User defined names:
letters, numbers, underscores (‘_’)
start with a letter

13.VHDL structure
Library
Definitions, constants
Entity
Interface
Architecture
Implementation, function

14.Design using VHDL
Define the logic function
    output   <=   inputa   and   inputb;
output is assigned to be inputa AND inputb
LHS contains only 1 variable only
RHS can be logics operations for many variables

15.Signal
All internal variables
Signal X,Y : std_logic;

16.Final code

17.Port Map

18.Process

19.All statements in a process occur sequentially if statements are defined in a process statement
Processes have sensitivity list

20.Modeling Digital Systems
VHDL is for coding models of a digital system...
Reasons for modeling
requirements specification
documentation
testing using simulation
formal verification
synthesis
class assignments
Goal
most ‘reliable’ design process, with minimum cost and time
avoid design errors!

21.Modeling the Dataflow way

22.Modeling the Behavior way
Architecture body
describes an implementation of an entity
may be several per entity
Behavioral architecture
describes the algorithm performed by the module
contains
process statements, each containing
sequential statements, including
signal assignment statements and
wait statements

23.Modeling the Structurural way
Structural architecture
implements the module as a composition of subsystems
contains
signal declarations, for internal interconnections
the entity ports are also treated as signals
component instances
instances of previously declared entity/architecture pairs
port maps in component instances
connect signals to component ports

24.Structural way...

25.VHDL Offers A Quicker Method For Logic Implementation.
Dramatically Reduces Logic IC Count In Digital Circuit Designs.
VHDL Uses A Modular Method of Design.
VHDL Is Widely Used Throughout Industry.