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Serial Peripheral Interface Presentation Transcript
1.Serial Peripheral Interface
2.SPI Features
Master/Slave
Supports up to 15 external devices
Supports SPI modes 0, 1, 2 & 3
All combinations of clock phase and polarity
Programmable:
8 to 16 bit Data Length
Delays between chip selects
Delays between consecutive transfers
Delays between clock and data per chip select
Selectable Mode Fault Detection
Fixed or Variable peripheral selection
Peripheral Data Controller (PDC)
Chained Buffer support
Local Loop back in Master mode
Master/Slave
Supports up to 15 external devices
Supports SPI modes 0, 1, 2 & 3
All combinations of clock phase and polarity
Programmable:
8 to 16 bit Data Length
Delays between chip selects
Delays between consecutive transfers
Delays between clock and data per chip select
Selectable Mode Fault Detection
Fixed or Variable peripheral selection
Peripheral Data Controller (PDC)
Chained Buffer support
Local Loop back in Master mode
3.SPI Block Diagram
4.Dependencies
PMC has to be programmed 1st for SPI to work
PIO Controller has to be programmed for the pins to behave as intended
SPI Peripheral Inputs “see” the state of the pad.
For example:
Use the SPI as a transmitter only.
Program the PIO controller pins for SPCK and MOSI to be outputs.
Program the PIO controller pin for MISO to be a GPIO.
The SPI peripheral’s internal MISO input will see the state of the GPIO.
Be careful of NPCS0/NSS/GPIO pin
If you only have 1 external SPI devices then technically you can don’t need an external chip select.
However if the SPI sees a 0 on NSS PIO line, a Mode Fault can be generated.
PMC has to be programmed 1st for SPI to work
PIO Controller has to be programmed for the pins to behave as intended
SPI Peripheral Inputs “see” the state of the pad.
For example:
Use the SPI as a transmitter only.
Program the PIO controller pins for SPCK and MOSI to be outputs.
Program the PIO controller pin for MISO to be a GPIO.
The SPI peripheral’s internal MISO input will see the state of the GPIO.
Be careful of NPCS0/NSS/GPIO pin
If you only have 1 external SPI devices then technically you can don’t need an external chip select.
However if the SPI sees a 0 on NSS PIO line, a Mode Fault can be generated.
5.Master Mode Clock Generation
6.SPI Control Register SPI_CR
7.Master Mode Shift Register
8.Mode Fault
9.Data Transfer Delays
Three delays can be programmed
Delay Between Chip Selects (DLYBCS)
Delays assertion from one chip select to another
Same delay for all chip selects
Delay Before SPCK (DLYBS)
SPCK is delayed after the chip select assertion
Programmable for each chip select
Delay Between Consecutive Transfers (DLYBCT)
Programmable for each chip select
Three delays can be programmed
Delay Between Chip Selects (DLYBCS)
Delays assertion from one chip select to another
Same delay for all chip selects
Delay Before SPCK (DLYBS)
SPCK is delayed after the chip select assertion
Programmable for each chip select
Delay Between Consecutive Transfers (DLYBCT)
Programmable for each chip select
10.Transfer Delays'
Delay Between Chip Selects (DLYBCS)
Use to accommodate SPI devices with long float times
Delay = # of MCK periods if FDIV = 0 or # of MCK periods * 32 if FDIV = 1
If DLYBCS < 6 its set to 6 to guarantee a minimum delay
Or 6 * 32 MCK periods if FDIV = 1
Delay Between Chip Selects (DLYBCS)
Use to accommodate SPI devices with long float times
Delay = # of MCK periods if FDIV = 0 or # of MCK periods * 32 if FDIV = 1
If DLYBCS < 6 its set to 6 to guarantee a minimum delay
Or 6 * 32 MCK periods if FDIV = 1
11.Transfer Delays'
Delay Before SPCK (DLYBS)
Defines delay from NPCS valid to 1st valid SPCK transition
If DLYBS = 0, the delay = ½ the SPCK period
Delay = # of MCK periods if FDIV = 0 or # of MCK periods * 32 if FDIV = 1
Delay Before SPCK (DLYBS)
Defines delay from NPCS valid to 1st valid SPCK transition
If DLYBS = 0, the delay = ½ the SPCK period
Delay = # of MCK periods if FDIV = 0 or # of MCK periods * 32 if FDIV = 1
12.Transfer Delays
13.Peripheral Selection
Fixed: PS bit in SPI_MR = 0
SPI manages data flow with only one external SPI device at a time
PDC uses optimal 8 or 16 bit data to transfer data – memory efficient
PCS field in SPI_MR used to select device on the bus
Variable: PS bit in SPI_MR = 1
SPI manages data flow with more than one external SPI device.
Using the PDC data is transferred in 32 bit mode.
32 bit SRAM locations are encoded to select the appropriate external device automatically.
Not as memory efficient but allows for multiple SPI device communication without processor intervention
PCS field in SPI_CSR0..3 select external devices on the SPI bus
SPI still manages the programmable data length of 8 to 16 bits in either mode.
Fixed: PS bit in SPI_MR = 0
SPI manages data flow with only one external SPI device at a time
PDC uses optimal 8 or 16 bit data to transfer data – memory efficient
PCS field in SPI_MR used to select device on the bus
Variable: PS bit in SPI_MR = 1
SPI manages data flow with more than one external SPI device.
Using the PDC data is transferred in 32 bit mode.
32 bit SRAM locations are encoded to select the appropriate external device automatically.
Not as memory efficient but allows for multiple SPI device communication without processor intervention
PCS field in SPI_CSR0..3 select external devices on the SPI bus
SPI still manages the programmable data length of 8 to 16 bits in either mode.
14.Peripheral Chip Select Decoding
PCSDEC bit in SPI_MR = 0
Chip selects NPCS0 – NPCS3 are directly connected to SPI devices
PCS field in SPI_MR maps directly to NPCS0 to NPCS3
1 of 4 encoding
PCSDEC bit in SPI_MR = 1
Chip selects NPCS0 – NPCS3 are connected to a 4 to 16 decoder
PCS field in SPI_TDR is binary encoded.
SPI_CSR0 controls external SPI devices 0-3, SPI_CSR1 controls …
Pins NPCS0 – NPCS3 at a logic 1 indicates no device selected
PCS value of 1111 is reserved for no transfers when PCSDEC = 1 or 0
15 external devices can be controlled when PCSDEC = 1
4 external devices can be controlled when PCSDEC = 0
PCSDEC bit in SPI_MR = 0
Chip selects NPCS0 – NPCS3 are directly connected to SPI devices
PCS field in SPI_MR maps directly to NPCS0 to NPCS3
1 of 4 encoding
PCSDEC bit in SPI_MR = 1
Chip selects NPCS0 – NPCS3 are connected to a 4 to 16 decoder
PCS field in SPI_TDR is binary encoded.
SPI_CSR0 controls external SPI devices 0-3, SPI_CSR1 controls …
Pins NPCS0 – NPCS3 at a logic 1 indicates no device selected
PCS value of 1111 is reserved for no transfers when PCSDEC = 1 or 0
15 external devices can be controlled when PCSDEC = 1
4 external devices can be controlled when PCSDEC = 0
15.Peripheral Chip Select Decoding PCSDEC = 0
16.Peripheral Chip Select Decoding PCSDEC = 1
17.Variable Peripheral Mode
18.Fixed/Variable & Chip Select Summary
Fixed
Communication managed with one peripheral at a time by the processor
Chip Selects controlled by SPI_MR
Memory efficient, processor in-efficient
Variable
Highly automated communication with up to 15 devices with no processor intervention
Chip Selects controlled by SPI_TDR, every write to SPI_TDR can select a different SPI device
Processor efficient, memory in-efficient
Chip Select Decoding
1 of 4 Encoding
Bit 0 of PCS field has priority
PCS = 0000 = NPCS0 = 0 NPCS 1-3 = 1
PCS = 0101 = NPCS1 = 0 NPCS 0,2,3 = 1
Binary Encoding
1111 not allowed
Fixed
Communication managed with one peripheral at a time by the processor
Chip Selects controlled by SPI_MR
Memory efficient, processor in-efficient
Variable
Highly automated communication with up to 15 devices with no processor intervention
Chip Selects controlled by SPI_TDR, every write to SPI_TDR can select a different SPI device
Processor efficient, memory in-efficient
Chip Select Decoding
1 of 4 Encoding
Bit 0 of PCS field has priority
PCS = 0000 = NPCS0 = 0 NPCS 1-3 = 1
PCS = 0101 = NPCS1 = 0 NPCS 0,2,3 = 1
Binary Encoding
1111 not allowed
19.Variable Peripheral Mode
Can you use Variable Peripheral Mode with only 4 external SPI devices?
Yes
Chip Select decoding has to be done by user’s SW.
PCS in SPI_CSR0..3 maps directly to NPCS pins
Software can create bus contention.
Can you use Variable Peripheral Mode with only 4 external SPI devices?
Yes
Chip Select decoding has to be done by user’s SW.
PCS in SPI_CSR0..3 maps directly to NPCS pins
Software can create bus contention.
20.Slave Mode
Slave mode characteristics defined by SPI_CSR0
RDRF in SPI_SR rises on transfer from Shift Register to Read Data Register
If RDRF is already high, transfer is aborted, OVRES bit is set
When a transfer starts, data shifted out is what’s present in the shift register
Slave mode characteristics defined by SPI_CSR0
RDRF in SPI_SR rises on transfer from Shift Register to Read Data Register
If RDRF is already high, transfer is aborted, OVRES bit is set
When a transfer starts, data shifted out is what’s present in the shift register
21.SPI Peripheral Data Controller
DMA from memory to peripheral and vice versa
Can be external memory on EBI for those parts that have an EBI
1 Master Clock Cycle needed for memory to peripheral transfer
2 Master Clock Cycles needed for peripheral to memory transfer
For each channel
32 bit memory pointer (incremented by byte, half-word or word)
16 bit transfer count (decrements)
32 bit next memory pointer (incremented by byte, half-word or word)
16 bit next transfer count (decrements)
Registers
Receive Pointer Register (RPR) and Transmit Pointer Register (TPR)
Receive Counter Register (RCR) and Transmit Counter Register (TCR)
Receive Next Pointer Register (RNPR) and Transmit Next Pointer Register (TNPR)
Receive Next Counter Register (RNCR) and Transmit Next Counter Register (TNCR)
DMA from memory to peripheral and vice versa
Can be external memory on EBI for those parts that have an EBI
1 Master Clock Cycle needed for memory to peripheral transfer
2 Master Clock Cycles needed for peripheral to memory transfer
For each channel
32 bit memory pointer (incremented by byte, half-word or word)
16 bit transfer count (decrements)
32 bit next memory pointer (incremented by byte, half-word or word)
16 bit next transfer count (decrements)
Registers
Receive Pointer Register (RPR) and Transmit Pointer Register (TPR)
Receive Counter Register (RCR) and Transmit Counter Register (TCR)
Receive Next Pointer Register (RNPR) and Transmit Next Pointer Register (TNPR)
Receive Next Counter Register (RNCR) and Transmit Next Counter Register (TNCR)
22.SPI PDC Chaining Buffers
Transmit Channel Example
When SPI_TCR = 0
Contents of SPI_TNPR are loaded into SPI_ TPR
Contents of SPI_ TNCR are loaded into SPI_ TCR
SPI_ TNCR is set to 0
Flags are updated accordingly
Transmit Channel Example
When SPI_TCR = 0
Contents of SPI_TNPR are loaded into SPI_ TPR
Contents of SPI_ TNCR are loaded into SPI_ TCR
SPI_ TNCR is set to 0
Flags are updated accordingly
23.SPI PDC Flags
ENDRX is set when RCR = 0
RXBUFF is set when RCR = 0 & RNCR = 0
ENDTX is set when TCR = 0
TXBUFE is set when TCR = 0 & TNCR = 0
How do you program the PDC to exceed 131,070 transfers?
Program SPI, Including Interrupt
Load 0xFFFF into both RCR & RNCR
Load memory pointers RPR & RNPR
Enable PDC channel
When ENDRX -> 1
Interrupt gets generated
Check RNCR = 0
Load RNCR with another value
Load RNPR with the next address
ENDRX is set when RCR = 0
RXBUFF is set when RCR = 0 & RNCR = 0
ENDTX is set when TCR = 0
TXBUFE is set when TCR = 0 & TNCR = 0
How do you program the PDC to exceed 131,070 transfers?
Program SPI, Including Interrupt
Load 0xFFFF into both RCR & RNCR
Load memory pointers RPR & RNPR
Enable PDC channel
When ENDRX -> 1
Interrupt gets generated
Check RNCR = 0
Load RNCR with another value
Load RNPR with the next address
24.SPI PDC Control & Status
25.SPI PDC Register Locations
26.SPI Interrupts
SPI Interrupt Enable Register SPI_IER (Write Only)
0 = No effect
1 = Enable
SPI Interrupt Disable Register SPI_IDR (Write Only)
0 = No effect
1 = Disable
SPI Interrupt Mask Register SPI_IMR (Read Only)
0 = Not enabled
1 = Enabled
SPI Interrupt Enable Register SPI_IER (Write Only)
0 = No effect
1 = Enable
SPI Interrupt Disable Register SPI_IDR (Write Only)
0 = No effect
1 = Disable
SPI Interrupt Mask Register SPI_IMR (Read Only)
0 = Not enabled
1 = Enabled
27.SPI Interrupts
28.SPI Status Register SPI_SR
Receive Data Register Full
Transmit Data Register Empty
Mode Fault Error
Overrun Error
End of Receive Buffer
End of Transmit Buffer
Receive Buffer Full
Transmit Buffer Empty
NSS Rising
Transmit Registers Empty
SPI Enable Status10
Receive Data Register Full
Transmit Data Register Empty
Mode Fault Error
Overrun Error
End of Receive Buffer
End of Transmit Buffer
Receive Buffer Full
Transmit Buffer Empty
NSS Rising
Transmit Registers Empty
SPI Enable Status10
29.SPI Summary
High Speed. 55 Mb/s for SAM7S devices
Separate baud rate generation on each chip select
Can control up to 15 external SPI devices
Programmable data length of 8 to 16 bits
Highly flexible automated DMA support
Put the processor to sleep while transferring data
Programmable delays on chip selects to accommodate various bus timing from different SPI IC manufacturers
Error checking
Local Loop Back
Mode Fault Detection
High Speed. 55 Mb/s for SAM7S devices
Separate baud rate generation on each chip select
Can control up to 15 external SPI devices
Programmable data length of 8 to 16 bits
Highly flexible automated DMA support
Put the processor to sleep while transferring data
Programmable delays on chip selects to accommodate various bus timing from different SPI IC manufacturers
Error checking
Local Loop Back
Mode Fault Detection
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