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ARM Programming Presentation Transcript
1.ARM Programming
2.ARM programmer model
The state of an ARM system is determined by the content of visible registers and memory.
A user-mode program can see 15 32-bit general-purpose registers (R0-R14), program counter (PC) and CPSR.
Instruction set defines the operations that can change the state.
The state of an ARM system is determined by the content of visible registers and memory.
A user-mode program can see 15 32-bit general-purpose registers (R0-R14), program counter (PC) and CPSR.
Instruction set defines the operations that can change the state.
3.Instruction set
ARM instructions are all 32-bit long (except for Thumb mode). There are 232 possible machine instructions. Fortunately, they are structured.
ARM instructions are all 32-bit long (except for Thumb mode). There are 232 possible machine instructions. Fortunately, they are structured.
4.Features of ARM instruction set
Load-store architecture
3-address instructions
Conditional execution of every instruction
Possible to load/store multiple register at once
Possible to combine shift and ALU operations in a single instruction
Load-store architecture
3-address instructions
Conditional execution of every instruction
Possible to load/store multiple register at once
Possible to combine shift and ALU operations in a single instruction
5.Instruction set
6.Data processing
Arithmetic and logic operations
General rules:
All operands are 32-bit, coming from registers or literals.
The result, if any, is 32-bit and placed in a register (with the exception for long multiply which produces a 64-bit result)
3-address format
Arithmetic and logic operations
General rules:
All operands are 32-bit, coming from registers or literals.
The result, if any, is 32-bit and placed in a register (with the exception for long multiply which produces a 64-bit result)
3-address format
7.Arithmetic
8.Bitwise logic
9.Comparison
10.These instructions do not generate a result, but set condition code bits (N, Z, C, V) in CPSR. Often, a branch operation follows to change the program flow.
11.Shifted register operands
One operand to ALU is routed through the Barrel shifter. Thus, the operand can be modified before it is used. Useful for dealing with lists, table and other complex data structure. (similar to the displacement addressing mode in CISC.)
One operand to ALU is routed through the Barrel shifter. Thus, the operand can be modified before it is used. Useful for dealing with lists, table and other complex data structure. (similar to the displacement addressing mode in CISC.)
12.Logical shift left
13.Multiplication
14.Features:
Second operand can’t be immediate
The result register must be different from the first operand
If S bit is set, C flag is meaningless
Second operand can’t be immediate
The result register must be different from the first operand
If S bit is set, C flag is meaningless
15.Data transfer instructions
Move data between registers and memory
Three basic forms
Single register load/store
Multiple register load/store
Single register swap: SWP(B), atomic instruction for semaphore
Move data between registers and memory
Three basic forms
Single register load/store
Multiple register load/store
Single register swap: SWP(B), atomic instruction for semaphore
16.Single register load/store
17.Load an address into a register
The pseudo instruction ADR loads a register with an address
The pseudo instruction ADR loads a register with an address
18.Application
19.Multiple register load/store
Transfer large quantities of data more efficiently.
Used for procedure entry and exit for saving and restoring workspace registers and the return address
Transfer large quantities of data more efficiently.
Used for procedure entry and exit for saving and restoring workspace registers and the return address
20.Multiple load/store register
21.Application
22.Control flow instructions
23.Branch conditions
24.Branch and link
25.Conditional execution
26.Instruction set
27.ARM assembly program
28.Add two numbers
29.Find larger of two numbers
30.GCD
31.Subroutines
32.Instruction set
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