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ARM Architecture Presentation Transcript
1.The ARM Architecture
2.Principle:
Programmers Model
Instruction Set
System Design
Development Tools
Programmers Model
Instruction Set
System Design
Development Tools
3.ARM Powered Products
4.Intellectual Property
ARM provides hard and soft views to licencees
RTL and synthesis flows
GDSII layout
Licencees have the right to use hard or soft views of the IP
soft views include gate level netlists
ARM provides hard and soft views to licencees
RTL and synthesis flows
GDSII layout
Licencees have the right to use hard or soft views of the IP
soft views include gate level netlists
5.Data Sizes and Instruction Sets
The ARM is a 32-bit architecture.
Most ARM’s implement two instruction sets
32-bit ARM Instruction Set
16-bit Thumb Instruction Set
Jazelle cores can also execute Java bytecode
The ARM is a 32-bit architecture.
Most ARM’s implement two instruction sets
32-bit ARM Instruction Set
16-bit Thumb Instruction Set
Jazelle cores can also execute Java bytecode
6.Processor Modes
The ARM has seven basic operating modes:
User : unprivileged mode under which most tasks run
FIQ : entered when a high priority (fast) interrupt is raised
IRQ : entered when a low priority (normal) interrupt is raised
The ARM has seven basic operating modes:
User : unprivileged mode under which most tasks run
FIQ : entered when a high priority (fast) interrupt is raised
IRQ : entered when a low priority (normal) interrupt is raised
7.Undefined : used to handle undefined instructions
System : privileged mode using the same registers as user mode
Supervisor : entered on reset and when a Software Interrupt instruction is executed
Abort : used to handle memory access violations
System : privileged mode using the same registers as user mode
Supervisor : entered on reset and when a Software Interrupt instruction is executed
Abort : used to handle memory access violations
8.The ARM Register Set
9.Register Organization
10.The Registers
ARM has 37 registers all of which are 32-bits long.
1 dedicated program counter
1 dedicated current program status register
5 dedicated saved program status registers
30 general purpose registers
ARM has 37 registers all of which are 32-bits long.
1 dedicated program counter
1 dedicated current program status register
5 dedicated saved program status registers
30 general purpose registers
11.Program Status Registers
12.Exception Handling
When an exception occurs, the ARM:
Copies CPSR into SPSR_<mode>
Sets appropriate CPSR bits
Change to ARM state
Change to exception mode
Sets PC to vector address
To return, exception handler needs to:Restore CPSR from SPSR_<mode>
Restore PC from LR_<mode>
When an exception occurs, the ARM:
Copies CPSR into SPSR_<mode>
Sets appropriate CPSR bits
Change to ARM state
Change to exception mode
Sets PC to vector address
To return, exception handler needs to:Restore CPSR from SPSR_<mode>
Restore PC from LR_<mode>
13.Development of the ARM Architecture
14.Condition Codes
15.Data processing Instructions
16.The Barrel Shifter
17.Using the Barrel Shifter: The Second Operand
18.Multiply
19.Single register data transfer
20.LDM / STM
21.Software Interrupt (SWI)
22.ARM Branches and Subroutines
23.Thumb
24.Example ARM-based System
25.AMBA
26.The RealView Product Families:
27.ARM Debug Architecture
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