PPT ON AVR RISC

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AVR RISC   Presentation Transcript

1.What does AVR RISC mean?
The acronym AVR has been reported to stand for: Advanced Virtual RISC and also for the chip's designers: Alf-Egil Bogen and Vegard Wollan who designed the basic architecture at the Norwegian Institute of Technology.
RISC stands for reduced instruction set computer.
    CPUdesign with a reduced instruction set as well as a simpler set of instructions (like for example PIC and AVR)

2.A Little History
The PIC (Programmable Interrupt Controller) appeared around 1980.
    8 bit bus
     executes 1 instruction in 4 clk cycles
     Harvard architecture
    
AVR (1994)
    8 bit bus
    one instruction per cycle
    Harvard architecture
 

3.AVR 8-Bit RISC High Performance
True single cycle execution
Single-clock-cycle-per-instruction execution
PIC microcontrollers take 4 clock cycles per instruction
One MIPS (mega instructions per second) per MHz
Up to 20 MHz clock
32 general purpose registers
Provide flexibility and performance when using high level languages
Prevents access to RAM
Harvard architecture
Separate bus for program and data memory

4.AVR 8-Bit RISC Low Power Consumption
1.8 to 5.5V operation
use all the energy stored in your batteries
A variety of sleep modes
AVR Flash microcontrollers have up to six different sleep modes
fast wake-up from sleep modes
Software controlled frequency

5.AVR 8-Bit RISC Compatibility
AVR® Flash microcontrollers share a single core architecture
use the same code for all families
1 Kbytes to 256 Kbytes of code
8 to 100 pins
all devices have
Internal oscillators

6.AVR: Good Documentation
Wide use
AVRFreaks .net
Free software

7.Status Register (SREG)
C: Carry Flag
Z: Zero Flag
N: Negative Flag
V: Two’s complement overflow indicator
S: N +V, For signed tests
H: Half Carry Flag ,T: Transfer bit used by BLD and BST instructions.
I: Interrupt Enable/Disable Flag

8.Registers and Operands
Rd: Destination (and source) register
Rr: Source Register
R: Result after instruction is executed
K: Constant data
b: Bit in Register File or I/O Register
s: Bit in the Status Register (3-bit)
X, Y, Z: Indirect Address Register
A: I/O location address
q: Displacement for direct addressing (6-bit)

9.The Program and Data Addressing Modes
RISC MC supports powerful and efficient addressing modes for access to the Program memory (Flash) and Data memory (SRAM, Register file, I/O Memory, and extended I/O Memory).
In the following figures, OP means the operation code part of the instruction word.

10.Register Direct
Register Direct, Single Register Rd : Register Direct, Single Register Rd E.g. Inc Rd  
Register Direct, Two Registers Rd and Rr : Register Direct, Two Registers Rd and Rr Operands are contained in register r (Rr) and d(Rd). The result is stored in register d (Rd). E.G ADD Rd, Rs

11.AVR I/O Memory Map
Peripherals and Ports are I/O mapped
Use IN/OUT instructions to access
Excerpt from I/O map showing ports:

12.AVR Data Memory Map: Part 1

13. AVR Addressing Modes
Register Direct, with 1 and 2 registers
I/O Direct
Data Direct
Data Indirect
with pre-decrement
with post-increment
Code Memory Addressing

14.Register Direct: 1 Register

15.I/O Direct

16.Data Direct

17.Data Indirect w/ Displacement

18.Data Indirect: Pre-Decrement

19.Data Indirect: Post-Increment

20.Prog. Memory Addressing

21.Indirect Program Addressing

22.Relative Program Addressing

23.I/O Register $3F : SREG

24.Instruction Examples: Add
Math
Add
ADD Rd, Rr – Adds two registers
Rd <- Rd + Rr
ADC Rd, Rr – Add with Carry two registers
Rd <- Rd + Rr + C
ADIW Rdl, K – Add Immediate to Word
Rdh:Rdl <- Rdh:Rdl + K

25.Other Math and Logic
Subtract
Logical AND
Logical OR
Exclusive OR
One’s Complement
Two’s Complement
Increment/Decrement
Set/Clear Registers and Bits in Registers

26.Branch Instructions
RJMP/RCALL – Relative Jmp (+/-k)
IJMP/ICALL – Indirect Jmp (Z Reg)
RET/RETI – Return from call/interrupt
CP* - Compare
SB* - Skip if Bit in Register or I/O is set/clr
BR* - Branch if condition is met

27.Other Instructions
NOP – Do nothing for 1 cycle
SLEEP – Sleep until reset or interrupted
WDR – Watch Dog Reset